As is known, isolation between multiple devices on a single semiconductor chip is one of the most important issues during fabrication. This is especially true as device dimensions decrease using sub-half and sub-quarter micron processes which allow an increase in device density on the chip real estate.
One common technique for isolation is known as local oxidation of silicon (LOCOS). In this technique, a window is opened between devices which allows oxygen to react with the silicon exposed under the window. The result is a "bowl" shaped oxide having a "bird's beak" at both sides to isolate devices on either side of the LOCOS oxide. However, do the resulting "bird's beak" and bowl shaped oxide, LOCOS is not practical (i.e. too large) for use in sub-half and sub-quarter micron fabrication processes.
Therefore, a newer technique known as shallow trench isolation (STI) has been developed to isolate such small dimension devices beyond 0.25 .mu.m. A conventional STI process is illustrated in FIGS. 1A-1C. In brief, a pad oxide layer 30 is grown on a silicon wafer 5. A silicon nitride layer 25 is then deposited on pad oxide layer 30 and acts as an polish-stop layer in subsequent CMP. As shown in FIG. 1A, photoresist 20 is patterned, e.g. by photolithography, over the selected active regions 15. The polish-stop and pad oxide layers 25, 30 are then etched between photoresist 20. Shallow trenches 10, 35 are then etched into wafer 5.
FIG. 1B shows a trench filling oxide dielectric layer 40 lining the chip surface. Note that a step 45 forms between the dense active areas 15 and the open area 35. This step forms the so-called "dishing" effect which occurs after CMP. FIG. 1C shows the chip after CMP having the dishing effect. Chemical-mechanical polishing may be performed using conventional slurry techniques, and the like. CMP serves a dual function; the first is planarizing the chip (although the dishing effect remains) and the second is to remove the oxide dielectric layer from the nitride polish-stop layer over active areas 15. As stated, nitride layer 25 acts as the polish-stop during the CMP step.
To reduce the dishing effect caused by CMP, a prior art technique using reverse-tone etch-back is known. This technique is illustrated in FIGS. 2A-2C. Reverse-tone mask 50, which has the opposite pattern as photoresist mask 20 of FIG. 1A, is formed between the active areas of the chip, as shown in FIG. 2A. Next, the oxide dielectric layer is etched away from the nitride polish-stop layer 25. However, due to the low etching selectivity rate between the oxide dielectric layer and the nitride layer (less than three), removing the oxide from the nitride is difficult at best. This is illustrated in FIG. 2B, showing a portion of the nitride polish-stop layer 25 etched away. To prevent the etching away of nitride layer 25, an alternative is to halt etching prior to reaching nitride layer 25, as shown in FIG. 2C. However, leaving a portion of the oxide on nitride layer 25 creates process control instability. Accordingly, neither scenario of FIGS. 2B or 2C is acceptable.
It is therefore an object of the present invention to improve the planarity of the chip using CMP during STI processes.
Another object of the present invention is to improve the etching selectivity rate between the nitride polish-stop layer and the overlaying oxide dielectric.
Various other objects, advantages and features of the present invention will become readily apparent from the ensuing detailed description and the novel features which will be particularly pointed out in the appended claims.